HIGH-SPEED CONFLICT-FREE LAYERED LDPC DECODER FOR THE DVB-S2, -T2 AND -C2 STANDARDS

International audienceLayered decoding is known to provide efficient and highthroughput implementation of LDPC decoders. However, the implementation of layered architecture is not always straightforward because of memory update conflicts in the a posteriori information memory. In this paper, we focus our attention on a particular type of conflict that is due to multiple-diagonal sub-matrices in the DVB-S2, -T2 and -C2 parity-check matrices. We propose an original solution that combines repetition of the concerned layers and the write disable of the a posteriori information memory. The implementation of this solution on an FPGA-based LDPC decoder led to an average air throughput of 200 Mbit/s with a parallelism of 45 and a clock frequency of 300 MHz. Increasing the parallelism to 120 led to an average air throughput of 720 Mbit/s with a clock frequency of 400 MHz on CMOS technology

Design of a GF(64)-LDPC Decoder Based on the EMS Algorithm

International audienceThis paper presents the architecture, performance and implementation results of a serial GF(64)-LDPC decoder based on a reduced-complexity version of the Extended Min-Sum algorithm. The main contributions of this work correspond to the variable node processing, the codeword decision and the elementary check node processing. Post-synthesis area results show that the decoder area is less than 20% of a Virtex 4 FPGA for a decoding throughput of 2.95 Mbps. The implemented decoder presents performance at less than 0.7 dB from the Belief Propagation algorithm for different code lengths and rates. Moreover, the proposed architecture can be easily adapted to decode very high Galois Field orders, such as GF(4096) or higher, by slightly modifying a marginal part of the design

Non-Binary Coded CCSK and Frequency-Domain Equalization with Simplified LLR Generation

International audienceIn this paper, we investigate the performance of Single-Carrier (SC) transmission with Non-Binary Low- Density Parity-Check (NB-LDPC) coded Cyclic Code-Shift Keying (CCSK) signaling in a multipath environment and we show that the combination of CCSK signaling and non-binary codes results in two key advantages, namely, improved Log-Likelihood Ratio (LLR) generation via correlations and reduced implementation complexity. We demonstrate that Maximum Likelihood (ML) demodulation can be expressed by two circular convolution operations and thus it can be processed in the frequency domain. Then, we propose a joint Frequency-Domain Equalization (FDE) and LLR generation scheme that aims at reducing the complexity of the receiver. Finally, we demonstrate through Monte-Carlo simulations and histogram analysis that this proposed CCSK signaling scheme gives more robustness to SC-FDE systems than commonly employed Hadamard signaling schemes (a gap of 1.5dB in favor of CCSK signaling is observed at BER = 10−5, assuming perfect Channel State Information)

Complexity Comparison of Non-Binary LDPC Decoders

International audienceThis paper presents a detailed complexity study of the existing non-binary LDPC decoding algorithms in order to rigorously compare them from a hardware perspective. The Belief Propagation algorithm is first considered as well as its derivative versions in the frequency and logarithm domains. We then focus on the Extended Min-Sum and its recent simplified version. For each algorithm, the number of operations in an elementary step of the check and variable nodes is determined. Finally we evaluate the interest of the application of the simplified Extended Min-Sum algorithm to a new family of non-binary LDPC codes designed in the framework of the DaVinci projec

Conflict Resolution by Matrix Reordering for DVB-T2 LDPC Decoders

International audienceLayered decoding is known to provide efficient and high-throughput implementation of LDPC decoders. However, the implementation of the layered architecture is not always straightforward because of the memory access conflicts in the a-posteriori information memory. In this paper, we focus our attention on a particular type of conflict introduced by the existence of multiple diagonal matrices in the DVB-T2 parity check matrix structure. We illustrate how the reordering of the matrix reduces the number of conflicts, at the cost of limiting the level of parallelism. We then propose a parity extending process to solve the remaining conflicts. Fixed point simulation results show coherent performance without modifying the layered architecture

Conflict resolution for pipelined layered LDPC decoders

International audienceMany of the current LDPC implementations of DVB-S2, T2 or WiMAX standard use the so-called layered architecture combined with pipeline. However, the pipeline process may introduce memory access conflicts. The resolution of these conflicts requires careful scheduling combined with dedicated hardware and/or idle cycle insertion. In this paper, based on the DVB-T2 example, we explain explicitly how the scheduling can solve most of the pipeline conflicts. The two contributions of the paper are 1) how to split the matrix to relax the pipeline conflicts at a cost of a reduced maximum available parallelism 2) how to project the problem of the research of an efficient scheduling to the well-known "Travelling Salesman Problem" and use a genetic algorithm to solve it

Design and implementation of a near maximum likelihood decoder for Cortex codes

International audienceThe Cortex codes form an emerging family among the rate-1/2 self-dual systematic linear block codes with good distance properties. This paper investigates the challenging issue of designing an efficient Maximum Likelihood (ML) decoder for Cortex codes. It first reviews a dedicated architecture that takes advantage of the particular structure of this code to simplify the decoding. Then, we propose a technique to improve the architecture by the generation of an optimal list of binary vectors. An optimal stopping criterion is also proposed. Simulation results show that the proposed architecture achieves an excellent performance/complexity trade-off for short Cortex codes. The proposed decoder architecture has been implemented on an FPGA device for the (24,12,8) Cortex code. This implementation supports an information throughput of 225 Mb/s. At a signal-tonoise ratio Eb/No=8 dB, the Bit Error Rate equals 2 × 10^−10, which is close to the performance of the Maximum Likelihood decoder

Pre-sorted Forward-Backward NB-LDPC Check Node Architecture

International audienceThis paper deals with reduced-complexity NB-LDPC check node implementation based on the Extended Min-Sum algorithm. We propose to apply a recently introduced pre-sorting technique to the forward-backward architecture. The pre-sorting of the check node inputs allows for significant complexity reduction. Simulation and synthesis results showed that this approach does not introduce any performance loss and can lead to significant area reduction in FPGA implementations (up to 54% for high check node degrees)

A new approach to optimise Non-Binary LDPC codes for Coded Modulations

International audienceThis paper is dedicated to the optimisation of Non-Binary LDPC codes when associated to high-order modulations. To be specific, we propose to specify the values of the non-zero NB-LDPC parity matrix coefficients depending on the corresponding check node equation and the Euclidean distance of the coded modulation. In other words, we explore the joint optimisation of the modulation mapping and the non-binary matrix. The performance gains announced by a theoretical analysis based on the Union Bound are confirmed by simulations results. We obtain an 0.2-dB gain in the high SNR regime compared to other state-of-the-art matrices

Advanced Coding Schemes for DNA-Based Data Storage Using Nanopore Sequencing Technologies

International audienc